The present disclosure relates to a semiconductor integrated circuit including a transistor having a fin structure, and a logic circuit including such a semiconductor integrated circuit.
It is known in the art that when a semiconductor integrated circuit is designed, the drivability of a transistor is controllable by adjusting the gate width or length of the transistor or changing the number of transistors connected in parallel to the transistor.
Japanese Unexamined Patent Application Publication No. H09-27554 discloses a semiconductor electronic circuit designed such that its drivability is controllable by arranging a plurality of transistors having different gate lengths and widths, selecting some transistors from these transistors depending on the necessity, and connecting such selected transistors together.
Recently, it has been proposed to utilize transistors a fin structure (hereinafter referred to as “fin transistors”) in the field of semiconductor devices. FIG. 6 schematically illustrates a fin transistor. Unlike a metal oxide semiconductor (MOS) transistor having a two-dimensional structure, its source and drain have a raised, three-dimensional structure called a “fin.” Its gate is disposed so as to wrap around a channel region defined between the source and drain in this fin. In this fin structure, the channel region is defined by three surfaces of the fin, thereby improving channel controllability significantly compared to conventional ones. As a result, various advantages, including reducing the leakage power, increasing the ON-state current, and lowering the operating voltage, are achieved. This leads to improving the performance of the semiconductor integrated circuit.